In sailplanes we add up to around 200 litres of water to wing tanks in single-seat gliders (empty weight typically around 280kg) to improve the high speed performance (typically up to 270 km/h these days) and ability to fly comfortably in turbulence.
It's surprising what you can fly formation with, even without an engine [1] :-)
[1] this particular glider does have a small engine for takeoff, but maximum speed with the engine extended is 180 km/h and here they are flying at 280 km/h.
Also from Stefan's channel, some fun here in New Zealand ... this flight passes just a couple of km from the Lord of the Rings "Weathertop" site (Google maps knows it).
> I still prefer programming the Z80 over the 6502 though :)
I really don't.
There are some few things you can fit into and get working fast in the Z80's A + 6 registers (IX and IY are not useful if speed is the aim), but for anything complicated the 6502's 256 Zero page locations — any pair of which can hold a pointer you can index off — is far superior.
The Z80 is awful at accessing memory for anything other than a simple absolute address or sequential access or push/pop of a register pair. It's better for manipulating 16 bit values, but not as much as you'd think especially once you run out of three register pairs plus ToS.
In the end, you could do memory load/stores with around 1 byte per microsecond on most home computers, no matter if 6502 or Z80. The Z80 did less work per clock, but was usually clocked 2..4x higher than 6502 based systems, which made up for the higher instruction cycle counts (the 2 MHz 6502 systems might have a slight edge against a 4 MHz Z80, but it wasn't night and day, and the C64 got away with its 1 MHz clock because the CPU was more or less just a controller for the various custom chips).
The 256 byte hardware stack is plenty for function return addresses and temporary use within a function. How deep are you planning to nest function calls anyway?
You can create as many other stacks as you want using pairs of Zero Page locations as stack pointers.
Best practice for recursive/reentrant code (e.g. compiling C) is to follow modern RISC/x86_64 practice and reserve a few (16 maybe) Zero Page locations as argument/working registers, a few (16 maybe) as callee-save registers, and have prolog and epilog utility functions that create/destroy a stack frame and save/restore N bytes of callee-save ZP locations.
You can unroll those into a sequence of elements like...
lda $1F
dey
sta (SP),y
lda $1E
dey
sta (SP),y
:
lda $10
dey
sta (SP),y
... at 5 bytes and 11 cycles per byte saved. And of course jump into the appropriate part of the sequence.
C-Sky and Andes NDS32 were popular enough to be supported by both GCC and the Linux kernel, both switched to RISC-V. ESP32 switched to RISC_V for all new chips.
Interestingly Synopsys's ARC's latest version ARC-V is RISC-V.
I think all major FPGA vendors now offer fully supported RISC-V soft cores either alongside their older proprietary ISAs or as the latest upgrade. Several (e.g. Microchip and Gowin) have included real RISC-V cores inside FPGAs.
There is zero chance that Apple doesn't have MacOS and iOS running on RISC-V in the lab.
They did that with x86 and Arm half a decade before any announcement about a switch, not to mention a number of other ISAs that didn't make it to shipping (e.g. M88k) and probably ones that word has never leaked about. IA64, anyone?
They're too large and rich and risk-averse to *not* do it.
Not me for sure. I have no idea about you. Of household name companies I've only worked at Mozilla and Samsung R&D. And SiFive if you count people in threads such as this.
I could of course be wrong but I think the publicly known history sets the pattern pretty reliably for the speculation.
What does this have to do with anything? You do know that a bunch of American corporations are shipping RISC-V cores, right? Including Jim Keller's current company, Tenstorrent.
Chinese scale is one way RISC-V could win. If China suddenly starts reaching <5nm process nodes at scale and uses RISC-V, they'd flood the market with cheap high performance RISC-V chips and probably start using them in their domestic Android phone market.
It's surprising what you can fly formation with, even without an engine [1] :-)
https://www.youtube.com/watch?v=G0icOICQLTc
Dumping (most of the) water before landing:
https://www.youtube.com/watch?v=I4Yv-V7eozk
[1] this particular glider does have a small engine for takeoff, but maximum speed with the engine extended is 180 km/h and here they are flying at 280 km/h.