I've worked in a start-up company similar to your company.
We developed a 256-cores RISC processor, only shared memory was used between all the cores instead of a mash-up of a memory block for each core and DMA for transactions.
How do you intend to synchronize work between the different cores? How a compiler will abstract away the memory synchronizations?
Which programming language is going to be used? So many questions as this is such a complex area in computing...
From my personal experience of over 5 years developing such chip in a start-up company, the cost of production will probably be a huge obstacle. Good luck!
Thanks! If you don't mind me asking, what was the name of the company?
Technically, you don't need to synchronize the cores... it's a MIMD/MPMD system that is not in lockstep. It is up to the programmer (with help from the compiler) to make sure you don't do anything too stupid ;)
As for the programming languages, C and Fortran are the big ones to us. We hope once our LLVM backend is improved, you'll be able to run anything you like on the cores themselves. As for the programming model, the three we like the best are CSP (Go), Actor (Erlang), and PGAS (C, Fortran, Chapel, a few other research ones). If you're familiar with SHMEM, that's the closest thing we can think of currently.
When it comes to cost, we're trying to develop as much ourselves to reduce licensing costs. We've been able to do a pretty good job (if I do say so myself) as just two people so far with no capital. Fabrication costs are the killer, with it being about ~$500k per shuttle run, and $5m-$7m for a mask set when we actually go to full production.
All our cores shared the same memory for both data and instruction and we based our synchronization of work-load on a hardware instead of software. It yielded such a huge speedup for execution time that most of the companies simply ignored our results as fake. :)
Choosing a programming language is crucial - we went with C and a declaration language for tasks. Today (4 years after we closed the company) I am not sure whether it was the best decision. The simpler the parallel definition in code the better. Programmers as getting confused easily.
I've worked in a start-up company similar to your company.
We developed a 256-cores RISC processor, only shared memory was used between all the cores instead of a mash-up of a memory block for each core and DMA for transactions.
How do you intend to synchronize work between the different cores? How a compiler will abstract away the memory synchronizations? Which programming language is going to be used? So many questions as this is such a complex area in computing...
From my personal experience of over 5 years developing such chip in a start-up company, the cost of production will probably be a huge obstacle. Good luck!